반도체 소자의 랜딩 플러그 형성 방법

Method for forming landing plug of semiconductor device

Abstract

A method for forming a landing plug of a semiconductor device is provided to prevent the generation of top bridge between landing plugs and to restrain the bridge due to a void of an interlayer dielectric by filling a nitride layer in an etched portion of the interlayer dielectric. An interlayer dielectric is formed on a semiconductor substrate in which a gate(110) is formed. The interlayer dielectric is partially etched by using a landing plug contact mask. A nitride layer(140) is filled in the etched portion of the interlayer dielectric. A landing plug hole is formed on the resultant structure by using the landing plug contact mask. A polysilicon layer is filled in the landing plug contact hole. A landing plug(150) is completed by planarizing the polysilicon layer.
본 발명은 반도체 소자의 랜딩 플러그 형성 방법에 관한 것으로, 랜딩 플러그 콘택 마스크 예정 영역을 노출시키고, 게이트 사이의 층간 절연막을 소정 깊이 식각한 후 상기 식각된 층간 절연막 부분을 질화막으로 매립하여 랜딩 플러그간의 탑 브릿지(Top Bridge) 및 층간 절연막에 발생하는 보이드(Void)에 의한 브릿지를 방지하는 기술을 개시한다.

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